Via: VIA Platform Implementation “Finding a better way to connect”
The combination of VIA chipset and Advanced- Communication-Riser card "ACR”
provides a proven solution for delivering cost effective audio and communication for
PC. This section exam the new ACR platform, which reduces the time to market and
system cost saving for PC manufacturers.
PCI SIG & IBTA: PCI-X and InfiniBand: I/O Evolution Advancing
This briefing will contrast and compare the perspectives from a member of the PCI
Special Interest Group and a representative from the InfiniBand steering committee.
Examine how each proposes to address the growing demands of scalability,
reliability, availability and performance needs of next generation server platforms.
VIA: DDR chipset roadmap “Revving up system performance”
This session provides a detailed description of key aspects of the VIA DDR chipset
features, partition, performance and preview of VIA future DDR chipset roadmap that
cover server, mainstream, SMA value desktop and mobile PC.
Micron: Designing Competitive DDR Platforms
A presentation of preferred design practice for implementing DDR DIMMs of
unbuffered, registered and small outline types. We will review the basics of DDR
subsystem design and share actual platform test results on channel margin and
signal integrity. We will also sort out the platform targets and finally present an
updated analysis of DDR power performance in power-critical applications such as
servers and notebook PC.
Micron: DDR Motherboard Design
This presentation covers DDR motherboard design using the Micron Samurai DDR
core logic. Topics covered include DDR memory channel overview, power generation,
and DDR memory channel routing. A few minutes are spent covering the DDR
memory channel and how it differs from standard synchronous DRAM. Power
generation covers the Vdd Vref and Vtt power sources required by DDR. The routing
rules section is a general discussion covering the requirements of placing and routing
the DDR memory bus.
Acer Labs: DDR Core Logic Solutions
DDR chip sets for AMD and Intel platforms: Examine design issues, trade-offs,
platform strategies and price/performance advantages over competing architectures.
Samsung: RDRAM, Today and Tomorrow
Required bandwidth and feature of memory subsystem will be discussed in
connection with memory technology. Key technical issues of RDRAM memory
subsystems in supporting high bandwidth operation will be presented in terms of
signal integrity, critical timing parameters, power consumption and so on. Future
RDRAM technology and corresponding technical challenges will be covered. Also,
industry status of RDRAM and anticipated trend will be presented.
Samsung: DDR, Today and Tomorrow
As the scope of high frequency applications broadens, the maximum bandwidth from
the memory system is of great importance. In this presentation, DRAM requirements
are evaluated in a memory system employing DDR SDRAMs for various applications.
Critical factors such as signal integrity, power and the frequency limitation are
considered. In addition DDR SDRAM's industry status and anticipated migration path
of DDR SDRAM will be presented.
NEC: Performance benefits of Virtual Channel Memory Architecture in Multi
Memory Master systems
Benchmark test results for multi-task systems with the Virtual Channel SDRAM
will be discussed. UMA systems using the most recent Graphics integrated
chipsets and Multi-CPU systems with the Virtual Channel SDRAM and normal
SDRAM are benchmarked and compared. Both synthetic benchmark and application
based benchmark program are used. Because of separate channels from DRAM
memory array, the Virtual Channel SDRAM can improve the performance of
multi-memory master systems such as UMA or Multi-CPU systems.
Acer Labs: Mobile Athlon Chipset with Power Now Technology
Technical rollout and full disclosure of the first mobile Athlon chipset. This session
will introduce the significance of Power Now technology, core logic feature sets,
price/performance analysis, etc.
Transmeta: Crusoe(tm) LongRun(tm) Adaptive Power Management Technology for Mobile
Platforms
Transmeta Crusoe(tm) processors incorporate an adaptive power management
technology called LongRun(tm) that dynamically adjusts processor performance (core
frequency) and power consumption (core voltage) to the optimal levels for the
workloads being executed. This presentation describes Transmeta's innovative
LongRun(tm) power management technology and provides a comparison with
traditional clock-throttling power management schemes as well as recent two-step
power adjustment strategies.
ST Microelectronics: Delivering High Performance, Affordable 3D Graphics - A First Look at the new
KRYO™ Graphics Accelerator
The presentation will review how increasing scene complexity and screen resolutions
are creating a memory bottleneck for conventional 3D accelerators. We will then review
how KYRO's PowerVR(TM) Tile Based Rendering technology improves memory
efficiency and image quality by keeping key operations on chip.
AMD: Turbocharging AMD-Athlon(tm) Platform with DDR Memory
This discussion will focus on AMD's platform strategies and technologies to maintain
its leading position in the PC desktop and workstation performance market.
JEDEC: DDR II: The Evolution Continues
Migrating a platform from DDR to DDR II. Spec update, platform design
considerations.