Paul DeMone van RealWorld Technologies heeft weer een erg interessant artikeltje online gezet, waarin hij de toekomst perspectieven van de 64-bit processors van Intel, Sun, MIPS / SGI, Compaq, IBM en Hewlett Packard bespreekt. Afgezien van MIPS, dat door Silicon Graphics inmiddels aan de kant is gezet voor IA-64, hebben al deze fabrikanten interessante plannen met hun 64-bit architecturen. Intel brengt later dit jaar de eerste IA-64 processors op de markt. HP voert een dualistisch beleid door zowel de eigen PA-RISC als de in samenwerking met Intel ontwikkelde IA-64 processors op de roadmap te houden. Sun introduceert in het derde kwartaal de lang verwachte UltraSparc III en IBM gooit hoge ogen met de dual core Power4 processor. Performance leider Compaq hoopt zijn posititie te consolideren door de release van de 21364 en nieuwe Alpha 21264 varianten.
Het wordt interessant om te zien wat Intel weet te bereiken met de IA-64. De performance van deze processors valt of staat met de kwaliteit van de compiler:
The basic underlying idea of IA-64, which its creators call EPIC (Explicitly Parallel Instruction Computing), goes back nearly 11 years to a research project started at HP Labs. At the time the first superscalar processors were being designed and a lot of effort was being expended to understand how to design out-of-order execution processors for the next generation to follow. It is quite ironic that the thinking that led to the hideously complex IA-64 architecture originated as a retreat to the keep-it-simple-stupid (KISS) design principles of the early RISC era in reaction to the daunting challenges faced by superscalar pioneers. EPIC proponents were seduced by the siren call of using Very Long Instruction Word (VLIW) like techniques to be able to build very wide issue processors using minimal control logic. There is no free lunch however, and the downside to EPIC is the reliance on the compiler to practically be clairvoyant in its ability to predict the optimal instruction scheduling strategy. No one has yet coded an algorithm to predict the future so the general compiler strategy is actually to generate code that runs as fast as possible for the execution path, predicted at runtime, to be the most likely. The compiler also has to generate code to check for when these assumptions made at compile time fail, and patch up the computational state sufficiently to generate the correct results, albeit more slowly.
The comparison between EPIC designs like IA-64, and dynamically scheduled superscalar processors (CISC or RISC) is in many ways is similar to that between the centrally planned command driven economies of the old Soviet era and laissez-faire capitalism. With the self-assured arrogance of faceless central planners working on the their next five year plan, EPIC designers assumed that their clairvoyant compilers, combined with their wide issue, high clock rate but inflexible processor hardware would be good enough to overcome the more dynamic and adaptive CPUs of its competitors. The hardware of dynamically scheduled processors may not have the time, resources or instruction search width available to an EPIC compiler to search out potential opportunities for instruction level parallelism (ILP). But it has one huge advantage - the ability and opportunity to adapt in real time to unexpected changes in program and data flow during execution arising from external factors (cache or TLB misses, interrupts etc) or unusual program input combinations.