Via JC kwam ik bij deze posting op het message board van Lost Circuits, met een samenvatting van de presentatie die de JEDEC (Joint Electron Device Engineering Council) gisteren heeft gegeven over de toekomst van DDR SDRAM:
Here are a few of the take-home messages:DDR will be generally available and used by Q3 2000. DDR manufacturing costs are about 1.03 x those of current SDRAM, because the same fabs and burn-in tools can be used. it is directly evolving from SDRAM and only needs the addition of a few minor components like DLL and I/O controller needs no initial testing because the parts are there already and have been tested on SDRAM Same power requirements as SDRAM (actually DDR chips are running at 2.5 V as opposed to the 3.3V of SDRAM but they need a terminating resistor on the mainboard which makes up for the difference in power. backed by all major memory manufacturers 45 ns initial latency (after idle) as opposed to 65-70 ns in RAMBUS Projected market share for 2001: 35-40% RAMBUS will still continue but be restricted to the high end server market with a projected market share of about 8% or less because of
High initial latency >65ns high production costs (current pricing >$900 for 128 MB) specific frequency matching required for each CPU speed grade requires new RIMMs for each CPU upgrade (overclock) SDRAM will prevail in the lower end market
Transition to DDR2: Q1-2 2001 with over 6 GByte/sec transfer capability utilizing 4-channel VCM or ESDRAM technology.



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The new FC-PGA 500 / 550E CPU brings new performance levels to the Socket 370 platform. In a clock for clock comparison with the Katmai-based Pentium III, the FC-PGA takes full advantage of the ATC and advanced system buffering and shows a substantial lead, at least in business applications. The interesting aspect is that the FC-PGA is priced very competitively, albeit substantially higher than Celeron processors. However, it appears fair to claim that most of the FC-PGA processors have excellent overclocking potential and, at least 700 MHz should be achievable without problems, beyond that, it is the luck of the draw. One needs to keep in mind also, that pure clockspeed not always translates into higher performance since, even in a stable running system, we observed decreasing performance above 715 MHz which we interpret as the result of occasional cache misses rather than a limitation of the core itself. Increasing the core voltage to 1.65 - 1.7V did not increase achievable clock speeds, neither did it remedy the falling edge of benchmark scores or the variability thereof at clock frequencies of 730 MHz or beyond.