Sander Sassen van HardwareCentral heeft vanuit het Intel Developer Forum in San Jose wat info bij elkaar geharkt over de Intel Pentium 4 processor. In zijn preview lees je over neuheiten als Hyper Pipelined Technology, Execution Trace Cache en Streaming SIMD Extension 2 (SSE2) waarmee de P4 ons later dit jaar blij gaat maken:
With the introduction of a 20-stage pipeline in the Pentium IV, the longest ever implemented in an x86 CPU, Intel has found a way to run it at very high clockspeeds, in excess of 1.5 GHz. A longer pipeline can be used to increase a CPU’s clockspeed by trading off the number of stages against clockcycle duration. As an instruction is processed in stages, a 10-stage pipeline divides an instruction into 10 steps and takes 10 clockcycles to process the entire instruction; during every clockcycle a stage of the instruction is finished. Due to its 20-stage pipeline Pentium IV takes 20 clockcycles to finish one instruction, so very little processing is done within a single clockcycle and it can be very short.
[...] Another performance booster is the Trace Cache; a trace cache will try to store the instructions in the sequence in which they are executed. For example, if instruction A jumps from location 100 to instruction B at location 200, the trace cache will store B in a location right behind A. So the trace cache simplifies processing by making sure that instructions are in the right sequence.
[...] Overall, Intel has implemented some quite inventive solutions in the Pentium IV to attain clockspeeds in excess of 1.5 GHz. If properly supported and implemented, the new SSE2 instructions, the long pipeline, the trace cache and the improved branch prediction algorithms all contribute to a CPU that could turn out to be a wolf in sheep’s clothing.