Het gerucht van JC over de vertraagde release van de Pentium 4 blijkt bevestigd te worden door een analist van Salomon Smith Barney. Volgens SSB is de P4 met 8 weken gedelayed omdat de SDRAM chipset niet op tijd beschikbaar is, maar een vertraging vanwege tegenvallende yields zou ook een mogelijke verklaring kunnen zijn. Onderstaande info is afkomstig uit deze posting op het Silicon Investor message board:
Willy delay: The most interesting thing about JC's rumor is that SSB said that Willy might be delayed by the same amount- 8 weeks. SSB though said it would be because of chipset problems, citing the need for an SDRAM chipset. This makes no sence though, because 8 weeks is insufficient extra time to allow for crash chipset development, unless the decision was make many months ago, and there was some recent delay in the program.
My interpretation is that Willy isn't yielding the required speeds, pure and simple. Scumbria has pointed out the inherent clock skew problems in the double pumped ALU. (3GHz skew tolerances!) The 26 stage pipeline is also way out of line with common sense, and, some secret branch prediction algorithm not withstanding (that doesn't violate CPT symmetry!), will reduce overall performance.
We need to remind ourselves of "the pattern." Intel has screwed up every major technology project for the past 18 months. It's failure to execute, pure and simple. It's a classic case of a company who's lost its core focus, and best tech people, and now has pointy hair types running amuck.
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