Ace's Hardware heeft getracht wat conclusies te trekken uit het x86-64 .PDFje dat AMD vandaag aan software developers ter beschikking heeft gesteld. Volgens de voorlopige bevindingen van Ace's Hardware zijn er geen tekenen dat de 'Technical Floating Point' extensies waarover eerder o.a. door Paul Demone werd geschreven, onderdeel uit maken van de x86-64 ISA. In plaats hiervan heeft AMD mogelijk gekozen voor SSE als alternatief voor de brakke stack-based x87 instructieset:
I have been looking over AMD's x86-64 Programmers' Overview for the past little while and, interestingly enough, I have failed to find any documentation detailing the long-rumored Technical Floating-Point (TFP) extensions. By TFP, I am referring to AMD's floating-point flat register-file, as opposed to the stack-based x87.The legacy x87, necessary for binary compatibility, is one of the last outposts of inefficiency in current x86 MPUs like the Athlon and Pentium III. While x86 processors have mostly caught up to RISC implementations in integer performance through agressive out-of-order implementations, they still fall well behind in floating-point performance. Take SPECfp2000, for example. The 1 GHz Pentium III achieves a base score of 327, while the 833 MHz 21264 scores 599. Obviously, there is room for improvement, which brings us to our question: where are the Technical Floating Point instructions? While the x86-64 Programmers' Overview dedicates a chapter to integer instructions in 64-bit mode, the references made to floating-point instructions are rare:
" No changes have been made to x87 floating-point instructions, so those instructions are not covered here. "
In fact, the table listed on page 10 indicates no change in the floating-point register set. Eight 80-bit floating-point registers, shared by the MMX unit, are specified under both legacy and 64-bit modes. I can find no reference to TFP, and everything I can find seems to indicate there have been no changes for floating-point operations under x86-64.
I am speculating here that TFP may have been shelved for SSE, which is specified in the overview. There aren't any trademarks mentioned for SSE (technically iSSE, according to Intel), and there is no mention of 3DNow! either. So there's certainly a bit more to unravel... [break] The Register meldt ondertussen dat AMD steun heeft gekregen uit onverwachte hoek. Sun is 'very excited' over x86-64 en heeft al aangekondigd dat er een x86-64 port van Solaris beschikbaar komt. Da's minder prettig nieuws voor Intel, dat toch al niet blij was met moeizame verlopende ontwikkeling van de IA-64 Solaris port: [/break] AMD has released a manual in PDF format to allow software developers to migrate their code to its 64-bit Hammer microprocessor platform.
And, in one of twists and turns that makes the computer industry endlessly fascinating, it has enlisted the support of Sun Microsystems, which has endorsed the x86-64 architecture for its Solaris operating system.
Right up in the second paragraph of a press release issued by AMD, Sun VP for Solaris, Anil Gadre, says his company is "very excited" by Hammer technology.
Thanks Venator en Crack voor de links.
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