Techweb heeft een erg lekker artikeltje over de plannen die AMD gisteren op het Microprocessor Forum heeft gepresenteerd, waaronder de 'Lightning Data Transport' (alweer een koele naam ) architectuur die voor de SledgeHammer ontwikkelt wordt:
AMD will debut its X86-64 architecture Tuesday at the Microprocessor Forum in San Jose, complemented by its Lightning Data Transport (LDT) I/O architecture.
[...] Following years of catastrophic manufacturing flubs, AMD has set out to ensure that manufacturing the new chip will be the easiest piece of the puzzle. Adding 64-bit capabilities increases the die size only 5 percent over the approximately 104 sq. mm that a 32-bit Athlon requires, using a 0.18-micron process, Lapinski said. While AMD's timetable still calls for 0.18-micron manufacturing to begin at Fab 30 in Dresden, Germany, later this quarter, the company on Monday showcased an 800-MHz Athlon running on the new process.
More importantly, AMD said that the combination of a small die size and its 0.18-micron process will allow the company to pack more than one 64-bit X86 microprocessor on a single die [wow, kick ass! ]. That's important, given that X86 integer instruction performance is closing in on RISC chips, Lapinski said. Through IEEE-compliant, triple-operand, double-precision floating-point instructions that AMD is designing for the new architecture, the company hopes to eliminate the floating-point advantage of RISC chips as well, he said.
[...] When pairing more than one microprocessor on-chip, AMD will use undisclosed custom logic to manage the infrastructure. Off-chip, however, AMD has designed the custom LDT bus for I/O and coprocessor chips. The LDT is a bidirectional bus, either 8, 16, or 32 bits wide; the bit width is negotiable at the device's initialization. Data passes through multiple logical channels in up to eight links or bridges, which can be connected to several daisy-chained devices.
Meer info in dit artikel:
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