Many of the postulated benefits of the Itanium are due not to any inherent advantage of going from 32 to 64 bits, (unlike the moves from 8 to 16 to 32 bits) but from having the CPU execute several 8 to 32 bit operations in parrallel which is the VLIW paradigm or a sort of generalized 3DNow/SSE instruction set. It is providing a compiler that can parrallelize instructions in this way that has occupied Intel for many years as a compiler was developed to take advantage of the planned architecture of the Itanium.
What I find intriguing is that Sledgehammer may come out from the start with two cores per chip. 64 bits should handle any address requirements for a long time, and if instructions are provided to synchronize the cores to allow for 128 moves, loads, etc. AMD could be shipping a 128bit processor a few months after Intel ships its 64 bit processor. The dual cores would let the chip take advantage of years of development of multithreaded operating systems and compilers without so much as a re-compile. The synch instructions would let it move data at twice the per/clock rate of Itanium.