Er zijn nog twee sources die ik erg interessant vind in de beschrijving van de Cell processor.
"The Cell Architecture is designed specifically around network communication. Every design concept that has gone into the Cell Architecture is done to facilitate communications amongst various Cells. Every aspect of the Cell Architecture including processing, data storage, data manipulation, and general resource sharing, are all available to every Cell using the same ISA (Instruction Set Architecture). It is this massive multimedia intercommunication that will be the heart of the next generation playstation, or PS3 for simplicity. This constitutes a paradigm shift from conventional computer architecture, whereby intercommunication is an afterthought and every device is architecturally different. The Cell Architecture represents not only the future of multimedia computer design but the future of computer technology as a whole."
"The basic architecture is comprised of various Cells or PE (processing elements) which themselves are comprised of a processing unit (PU), a direct memory access controller (DMAC) and a multiple number of attached processing units (APUs). In a "preferred" embodiment (as the Patent outlined it), a PE comprises eight APUs.
The PU and the APUs interact with a shared dynamic random access memory (DRAM) preferably having a cross-bar architecture. The PU schedules and orchestrates the processing of data and applications by the APUs. The APUs perform this processing in a parallel and independent manner.
The DMAC controls accesses by the PU and the APUs to the data and applications stored in the shared DRAM. In accordance with this modular structure, the number of PUs employed by a device (PC, PS3, PDA, HDTV, HD-DVD, etc.) of the network is based upon the processing power required by that particular device. For example, a server may employ four PUs, a workstation may employ two PUs and a PDA may employ only one PU. The number of APUs of a PE assigned to processing a particular software cell (data and application to be processed) depends upon the complexity and magnitude of the programs and data within the cell."
"Basically, there are a number various types of devices or member Cells contained within a network (diag1). This network is comprised of all types of media / protocols and is on a WAN scale. However, there are two important commons involved. First, all member Cells transmit Software Cells via IP which allow for these SoftCells (for short) to be routed on any network. The second common; all of the member cells have a similar Instruction Set Architecture (ISA) to facilitate a distributed programming model for transmitting data and applications over a network, and for processing data and applications among the network's members. This programming model employs software cells transmitted over the network for processing by any of the network's member cells. Each software cell has the same structure and can contain both; instructions and data. As a result of the high speed processing and transmission speed provided by this modular computer architecture, these cells can be rapidly processed.
How Intercommunication Can Assist Processing
Softcells each contain a Global Identification (GID) and information describing the amount of computing resources required for that particular softcell's processing. Additionally, these softcells contain a date/time stamp to help provide sequence data to the Cell systems. Since all computing resources have the same basic structure and employ the same ISA, the particular resource performing this processing can be located anywhere on the network, and dynamically assigned. Meaning that, if a particular member cell is busier than another, the requesting softcell will be routed to the least utilized cell or "best metric" cell for processing. Keep in mind that the best metric can be a multitude of variables including distance, delay, processing load, multiple of PU's, etc."
En een ppt presentatie (yikes) waarin de architectuur wordt beschreven.
50M PS2s = 310 Petaflop, 5M PS3s = 5 Exaflops networked
Similar to streaming media processor
(SUN MAJC processor)
Small memories because data is flowing
Sony understands bus/memory can kill performance
Tools seem pretty difficult to make
Hard to wring out theoretical performance"