Ik kwam bij Ace's Hardware deze erg handig info tegen over de Motorola G4+, een opgevrolijkte verbouwing van de G4 processor die hogere kloksnelheden mogelijk moet maken. Tevens gaat Motorola, in navolging van Intel, een 256Kb groot L2 cache op de core plakken:
According to Microprocessorwatch's, Keith Diefendorff, a coarchitect of the beloved alti-vec instruction set Motorola have taped out the so called G4+ 2 monthes ago. This new chip as presented at uPF is a significant mid-age improvement upon the G4 core. First doing what Winchip did, they added pipeline stages to the orginal design, this is said to allow the core to scale past 700MHz on Motorola's 0.18um copper HIP6 process. Unlike Winchip who just added pipeline stages to get MHz, Motorola increased the instruction fetch/decode bandwidth from 3 to 4 (1 being a branch) beside adding a new integer excution unit for a wider machine. To further extract ILP from teh code, the added the instruction reorder buffer depth. These improvement is said to allow the G4 to maintain its brianiac per MHz performance while scale up its clock speed.
The other significant addition is the added 256KB ondie L2. Being fully pipelined at CPU speed, this cache boast 2X the bandwidth of Coppermine's L2. (22GB/s at 700MHz, vs 11GB/s at 700MHz for Coppermine, this also says that the bus is probabily 256bit wide) Yes, the apple users/Steve Jobs can rightfully claim that their L2 cache can feed twice the data to the core than Intel's at the same clock speed, if Intel cannot get Willaimette out first. Besides that the G4+ still have a backside L3 bus for an even better memory sub-system.