The Register heeft info over de IBM PowerPC Power4, een 64-bits processor die geïntroduceerd zal worden op snelheden van 1GHz en bestaat uit meer dan 200 miljoen transistors:
Power4 will have two microprocessors on a single piece of silicon, and at 1.1GHz should be able to deliver 11,000 MIPS. The architecture comes out of Austin, and chips will be fabbed at the Fishkill Semiconductor Center. [break] Volgens eerdere geruchten zou het chippie een bus van 500MHz krijgen. Geheugensnelheid begint echter steeds verder achter te raken op processor snelheid, en het is dan ook de vraag hoe IBM dit gaat fixen: [/break] Whatever the architecture or design, processors spend most of their time waiting for cache misses, so the optimised feeding of processors is the main performance challenge. Software design trends such as OOP and JIT compilation will increase the memory hierarchy load, so the design challenge is to deal with the memory hierarchy bandwidth.IBM says it believes that its approach to parallelism (Ultra SMP) is superior to Intel's EPIC since EPIC increases the demand for memory hierarchy bandwidth and low latency. IBM also claims that EPIC is less suitable for JIT Java compilation as it needs lengthy compilation and a large optimisation window. Another difficulty that IBM identifies with EPIC is in future binary compatibility, resulting in a probable need to recompile.
