PassMark Software heeft versie 11.0 van Memtest86 uitgebracht. Met dit programma kan het interne geheugen aan een rigoureuze test worden onderworpen om zo eventuele problemen aan het licht te brengen. Memtest86 is in 1994 door Chris Bradly ontwikkeld en begin 2000 is de wellicht nog bekendere Memtest86+ als een fork ontstaan, wat nogal eens tot verwarring leidt. Sinds 2013 is het eigendom van PassMark Software en is het beschikbaar in een gratis en twee betaalde uitvoeringen. Hieronder is de changelog voor deze uitgave te vinden:
New Features
- Added new configuration file parameter CHECKMEMSPEED for verifying whether the configured memory speed is consistent with one of the SPD profiles or an arbitrary minimum speed specified by the user. If this check fails, an error message is displayed and the memory test will not start.
- Added new configuration file parameter TCPREQUESTLOCATION for specifying the URL request path (and cloud API key) for PassMark Management Console integration
- Added new configuration file parameter TCPGATEWAYIP for setting the default gateway route IP address to allow for connections outside the local network for PassMark Management Console integration
- Added new configuration file parameter SPDREPORTEXTSN for specifying whether to use the module’s extended, 18-digit serial number or standard 8-digit JEDEC serial number in reports. The extended serial number encodes additional manufacture information (including the manufacture ID, date and location).
- Added new configuration file parameter DISABLESPD for disabling SPD collection. This is a workaround to prevent throttling of memory speeds resulting in increased test times. This occurs when reading SPD data interferes with the chipset’s Closed-Loop Thermal Throttling (CLTT) mechanism.
- Added new configuration file parameter TSODPOLL to enable/disable polling of DIMM temperature sensors (if available)
- Preliminary address module decoding support for Intel Meteor Lake/Arrow Lake chipsets
- Support for collecting memory timings periodically during the test session. When the test completes, the lowest/highest memory speeds are reported.
- Added support for reporting AMD EXPO profiles in DDR5 SPD
Fixes/Enhancements
- Added TLS support for PassMark Management Console integration
- Added DNS support for PassMark Management Console integration
- Added support for new DDR5 form factors “CDIMM”, “CSODIMM” and “CAMM2” for CHIPMAP configuration file parameter. This is to support the new clocked (CUDIMM/CSODIMM) and compact (CAMM2/LPCAMM2) DDR5 form factors supported by newer chipsets (eg. Intel Arrow Lake)
- Increased maximum string length of chip labels to 6 for CHIPMAP configuration file parameter. This is to support longer names used in CUDIMM, CSODIMM and CAMM2 component labels such as “DAR0B0”.
- Fixed bug in address module decoding on Intel Comet Lake chipsets
- Fixed incorrect channel mode detection for the following chipsets:
- AMD Ryzen
- Intel Coffee Lake
- Intel Comet Lake
- Intel Ice Lake
- Intel Rocket Lake
- Intel Tiger Lake
- Intel Elkhart Lake
- Fixed incorrect memory timings detection for the following chipsets:
- AMD Ryzen
- Intel Meteor Lake
- Intel Arrow Lake
- Intel Ice Lake-SP
- Intel Emerald Rapids-SP chipsets
- Fixed incorrect clock speed detection for the following chipsets:
- Intel Rocket Lake
- Intel Ice Lake
- Intel Tiger Lake
- Intel Alder Lake
- Intel Meteor Lake
- Intel Arrow Lake
- Intel Elkhart Lake
- Intel Ice Lake-SP
- Intel Emerald Rapids-SP
- Preliminary support for obtaining memory settings for the following AMD chipsets:
- AMD K8
- AMD K10
- AMD Bulldozer
- AMD Piledriver
- AMD Steamroller
- AMD Excavator
- AMD Jaguar
- AMD Puma
- Preliminary support for multithreading on ARM64, which was previously unavailable due to UEFI BIOS limitations
- Fixed issue with reading DDR5 SPD when the SPD page has not been reset to zero
- Fixed ECC injection option not available on AMD Ryzen Zen 3 chipsets. Note that in general ECC injection is not a feature that is normally accessible by end-users and typically requires a custom BIOS.
- Fixed In-band ECC (IBECC) capability detection on the following chipsets:
- Intel Tiger Lake
- Intel Alder Lake
- Intel Meteor Lake
- Intel Arrow Lake
- Intel Elkhart Lake
- Fixed ECC capability detection on Intel Ice Lake-SP and Emerald Rapids-SP chipsets
- Fixed reporting of invalid DIMM temperatures by adding checks for valid Temperature Sensor on DIMM (TSOD) raw data
- Added support for retrieving Intel Meteor Lake and Arrow Lake CPU information
- Updated Chinese and Japanese localization strings (courtesy of Nagisa)
- Updated blacklist to work around specific mainboards/BIOSes with known UEFI multithreading and other issues
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