Bij Target PC is wat meer info te vinden rondom de nieuwe Joshua processor van Cyrix (overgenomen voor VIA). Met features zoals support voor 66, 100 en 133MHz en unlocked clock multipliers kan dit weleens een erg goed overklokbaar CPU'tje worden :
First off the Joshua is in a socket 370 format which means it uses existing formats (slot 1 with converter card). Next is the support for 66-100-133 Mhz FSB, you know what this means, the clock multiplier is not locked. This processor can be used on mainboards with chipsets ranging from LX chipsets right up to the latest i840, using a slot converter card. Now Cyrix has entered the Intel only territory, pretty gutsy move don’t ya think?
The technical specs indicate the Joshua is as technically advanced as it’s competition, On die full speed L2 Cache (more on that later), .018u fabrication process, 3dnow!™ Technology, and "Enhanced dual pipelined MMX™ and FPU"!
The .018 fabrication process should pretty well guarantee that the Joshua would be an overclocker’s dream. The processor is supposed to be launched at a paltry 433 Mhz, why 433 you ask? This could be the backdoor attack that could bring Intel to its knees. The processor will be classed as an entry level CPU and it’s primary target is the Intel Celeron™, since the Celerons are .025u technology CPU’s the Joshua should become the new hotrod in the entry level arena. After all the Celeron wasn’t a popular processor until it was realized that they had overclocking potential that put them in the performance arena with their bigger brothers the PII-PIII. The Joshua should have a core tolerance of speeds in excess of 700+ Mhz. The best the Celeron cores can do is 600 Mhz on rare occasion. Hey! 700Mhz for the price of a 433? Now that is something that would catch the eyes of a lot of gamers/power junkies/ Overclockers, and hopefully PC manufacturers.
The L2 Cache is Full speed on die that is "Mutually exclusive". Well what the heck does that mean? It means that the 64kb L1 cache can share the 256k L2 cache’s memory, and vice versa. Now you have a 320K full speed cache that acts like a big L1 cache AND L2 Cache. Integer performance should be out of this world, and with the enhanced dual pipelined FPU (hopefully) the Trait that killed national semi conductor, could be gone.