Toshiba heeft een artikel gepost over hun in eigen huis ontwikkelde Fast Cycle RAM architectuur. Met FCRAM wil Toshiba vooral het latency probleem aan pakken, de peak bandwidth is gelijk aan DDR (2,1Gb/sec), terwijl de effectieve bandwidth volgens Toshiba respectievelijk 1165Mb/s (FCRAM) en 897Mb/s (DDR) bedraagt. Hier wat info over dit nieuwe geheugentype:
All of the DRAM types commonly discussed in the industry today, such as EDO, SDRAM, DDR and RDRAM, have one major thing in common ñ their memory cores are the same. What is different about each type is the peripheral logic circuitry, not the memory cell array. What this complex new peripheral logic circuitry does is attempt to hide the inherently slow memory core.
FCRAM is a novel concept, which finally recognizes and fixes the slow memory core by segmenting it into smaller arrays such that the data can be accessed much faster and latency greatly improved. How this is done is beyond the scope of this paper. If the reader is interested, both Toshiba and Fujitsu can provide more detailed information on FCRAM functionality.
The key measure of how FCRAM improves latency and can improve system performance is the read/write cycle time (tRC), which measures how long the DRAM takes to complete a read or write cycle before it can start another one. In the case of conventional DRAM types, including SDRAM, DDR and RDRAM, tRC is typically on the order of 70ns. With FCRAM, tRC of 20 or 30ns is possible. For this reason, this new device is referred to as a fast cycle RAM.
Besides faster tRC, FCRAM also improves latency with several new features that will be discussed below. [break] In hetzelfde artikel tevens info over DDR-II, dat ten opzichte van normaal DDR SDRAM een verdubbelde clock/data rate van 200/400MHz heeft. De peak bandwidth bedraagt 3,2Gb/s bij een busbreedte van 64-bit en 6,4Gb/s bij een 128-bit dikke bus: [/break] It should be noted that DDR in the above table is based on today's industry specification, which basically includes 100MHz and 133MHz clock rates. DDR-II is currently being defined by JEDEC, and is expected to offer much higher clock rates and features to improve effective bandwidth, some of which will be discussed below.
Based on the above analysis, DDR can match RDRAM in terms of peak bandwidth. However, the system designer must make the determination of which device to use based upon the advantages/disadvantages of widening the bus from 64 to 128 bits for DDR vs. adding multiple channels for RDRAM. Additionally, peak bandwidth is only one factor in determining effective bandwidth as was mentioned above and will be discussed further below.