Digit Life kreeg wat interessant info over de status van de Pentium 4 en Tehama chipsets toegespeeld. Volgens deze informatie wordt de P4 in de week van 26 november tot en met 2 december gereleased. De Tehama chipset blijkt nog over enkele bugs (errata) te beschikken, die te maken hebben met de interactie tussen de ICH2 (I/O Controller Hub) en de MCH (Memory Controller Hub) van de Tehama chipset. Het fixen van de problemen loopt op schema:
Intel Pentium 4 processor launch has been retargeted to WW48. Intel Pentium 4 processor development on track
A PCI interoperability issue has been identified with the Intel 850 chipset
- Hardware validation on track, looking good
The issue is completely understood and has been root caused
- Failures have been seen with certain PCI graphics cards
- This issue will be classified as an ICH2 erratum (only manifests itself with 850 MCH)
850/860 chipset erratum identified
- Due to interaction between the 850 MCH and ICH2
- Fix validated with FIB'd ICH2 Intel will implement a low risk stepping to the ICH2
- New Stepping is B1' (B1 prime)
- B1' samples expected to be avail WW42 and updated production commits WW41
- B1' stepping will not require any motherboard or BIOS changes
- Customers should continue validation efforts with the current ICH2 B1 step
- Customers encouraged to perform targeted regression testing on ICH2 B1' Does not affect Intel Pentium III processor based systems (with 810E, 815E, 820E)
Silicon fix to tie an existing logic signal in the ICH2 to the buffer invalidate logic
- During PCI memory read line or memory read multiple commands, the ICH2 will pre-fetch data from memory and may not invalidate the pre-fetched data(if required), thus allowing invalid data to be delivered to a PCI master
- Issue only occurs in 850/860 chipset based systems due to the unique architectural interactions between the MCH and the ICH2
- Minor metal layer fix
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