Dean Kent van Silicon Insider heeft wederom een interessante Industry Update gepost. Allereerst nieuws over de KX133:
On a positive note for AMD, it appears that there are quite a number of KX-133 based boards ready to be 'officially' announced in January. Wide availability of these boards combined with Fab 30 processor shipments in Q2 should give AMD an opportunity to grab some market share from Intel. Several manufacturers I have spoken with have some concerns of AGP support here as well (same core as the Pro133A), and plan on a more conservative approach by waiting until late January or early February. [break] Verder info over de AMD Spitfire, Thunderbird en Mustang:[/break] The most likely candidates for the Cu process are the Spitfire and Thunderbird processors. Though there has been no official confirmation of the configurations, it appears that Spitfire will be offered as a Socket A processor and will have 128K L2 cache. Thunderbird will likely be offered as both Slot A and Socket A, and will sport 256K to 512K L2 cache.
In Q3/Q4, the Mustang (Slot A & Socket A) will be introduced will have full-speed L2 cache, up to 2MB and will have a 266MHz FSB. This will be a 'low-power' processor and will be aimed at the high-end (servers and workstations). [break] Tenslotte een stukje over DDR SDRAM, waarvan verwacht wordt dat het de dominerende geheugen standaard is aan het eind van dit jaar: [/break] When Intel first capitulated and gave support to 133MHz SDRAM, they called it a 'transition' product between SDRAM and DRDRAM. It is safe to say that PC133 can still be called a transition product, but the transition is to DDR. Both VIA and AMD have announced their intention to include DDR support in upcoming chipsets. Micron has already demonstrated systems using their Samurai/Shark chipset using DDR SDRAM. They have also provided the design to other chipset manufacturers, including VIA.
Virtually all sources within the memory industry that I have spoken with have indicated that they believe DDR will be the dominant memory by the end of 2000, transitioning to DDR II sometime in 2001. The exciting thing about DDR II is that it will apparently be a packet based memory design, using some of the technology developed for SLDRAM.