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Bron: The Register

Motorola heeft op het Microprocessor Forum plannen gepresenteerd die de G4 processor beter geschikt moet maken voor hogere kloksnelheden. De G4 dobbert op dit moment namelijk nog op 450MHz, terwijl AMD (en binnenkort ook Intel) al vrolijk op 700MHz rondfietsen. Hier de info, grof geleend van The Register:

To date, the PowerPC's clock speed has been limited by the size of its processing pipeline. The current G4 has a four-stage pipeline -- the path of an instruction through the chip -- and that's not enough to keep a 700MHz CPU fed with instructions and data. Motorola could simply up the frequency, but the processor would have so much idle time that the speed advantage would be lost.

The second-generation G4 increases the pipeline to seven stages, and to counter the reduction in the number of instructions a processor can handle per second inherent in long pipeline, the company has increased the number of instruction processing units in the chip.

According to Naras Iyengar, one of the chip's design team leaders, the new G4 will feature two extra integer units, taking the total to four, in addition to the existing floating-point unit and four AltiVec units. The AltiVec system has been enhanced to handle two instructions simultaneously, each being automatically passed to the relevant unit according to the type of data involved.

Following a clear industry trend, the new G4 brings the L2 cache into the chip itself to allow it to operate at the same speed as the core. The L1 caches remain the same size -- 32K instruction, 32K data -- while the on-die L2 will be 256K, connected to the L1 via a fast 256-bit wide datapath (up from the 7400's 64-bit path). Like AMD's K6-III chip, the new G4 will also support a third layer of cache between the CPU and the main memory bank, in backside configuration. It will support up to 2MB of this L3 cache.

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