Ace's Hardware heeft een zooitje info gepost over de Sun UltraSparc III. Klinkt allemaal errug lekker:
Its most impressive point is the cache subsystem, unlike HP's PA-8500 which has 1.5MB L1 ondie, UltraSparcIII has 32KB instruction L1, 64KB Data L1, and 2KB each of Write and Prefetch cache, 4MB off die data L2, 8MB offdie instruction L2, with all ondie ones being 4way set associative, and all offdie ones being direct mapped. The L1 latency are 2 cycles, Prefetch 3 cycles, and L2 being 12 cycles. But its the bandwidth of these caches thats the most impressive, L1 data have 9.6GB/s, Prefetch have 18.4GB/s, L1 write have 13.6GB/s, L2 being 6.4GB/s, and memory interface which controls 4 banks of SDRAMs being 3.2GB/s. Also it allows 15 outstanding transactions per cycle from each processor which can complete out of order. So by doing this Sun assures that when the instructions observe no data dependency it can crank out lot of numbers by giving the processors lots of stuff to work on. The 16384 2bit branch predictor using Gshare algorithm is also one of the largest we have seem. L2 bus being 288bit and can fetch a whole cache line in one cycle. The ondie L2 tag also aloows quick miss detection. The instruction issue unit is 4 issue, with a 20 entry instruction queue. The integer excution unit have 4 pipelines and excutes most instructions in 1 cycle. The 4 pipelines are A0/A1 arithmetic, logical, shift unit (i assume one does add/sub, the other does mul/div, etc), 1 load/store, and 1 branch unit. The integer unit is 4 issue. The 2 issue floating point/graphics unit have 3 data pathes. Divide/multiply, add/subtract/compare, and an independent division data path, which lets a nonpipelined divide go through without blocking the mul pipeline. The latency on ADD and MUL are 4 cycles, divide being 20 cycles, and square root 24 cycles. the throughput are latency minus 3 cycles. (note these are all double percision 64bit stuff)
Hmm ja, leuk om een webservertje op te draaien!? (wij zijn nog op zoek naar sponsors ).