VIA heeft een press release het web op gezet waarmee we lekker worden gemaakt over hun HDIT (High-Bandwidth Differential Interconnect) architectuur voor de allernieuwste generatie VIA Apollo chipsets. De HDIT architectuur bestaat uit een north- en southbridge die zijn verbonden door middel van een V-Link bus die 512MB's per seconde kan verwerken. De northbridge heeft ondersteuning voor DDR266 geheugen, AGP 4x en 4 CPU’s. De southbridge is ook niet mis, er zitten o.a. dual ATA-100 controllers op en ook een LPC bus (wat dat ook moge zijn). Andere indrukwekkende getallen zijn: 4.2GB/sec memory bandwith en 2.1GB/sec tussen de northbridge en IO poorten met behulp van 2 optionele 64-bit HDIT PCI-X chips.
Zoals je ziet zijn de specs prima (zelfs goed, erg goed) en als de performance evengoed als de specs wordt dan lijkt me dit een zeer interessante chipset. Als de prijs ook nog een beetje gunstig wordt (jammer genoeg is de doelgroep de high-end desktop, workstation en server markt, iets wat geen goed teken is…) dan lijkt me dit een goede chipset om een single, of een dual systeempje rond te bouwen 
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VIA unveils High-Bandwidth Differential Interconnect Technology (HDIT) Architecture for next generation of VIA Apollo Chipsets
Provides flexible baseline mainstream PC platform that can be scaled to meet high bandwidth requirements for multiprocessor workstations & servers
Taipei, Taiwan, August 7th, 2000 -- VIA Technologies, Inc, the world's leading fabless supplier of PC core logic chipsets, microprocessors, and multimedia and communications chips, today unveiled its advanced new scaleable HDIT (High-Bandwidth Differential Interconnect) Architecture for its next generation of VIA Apollo DDR chipsets.
VIA's HDIT Architecture provides a cost-effective yet highly flexible baseline platform that allows System OEMs to integrate such advanced features as a DDR266 memory interface, AGP4X, and VIA's new 512MB per second V-Link bus to a highly-integrated HDIT South Bridge in mainstream desktop and mobile PC designs. To ensure the scalability that System OEMs require for high-end multi-processor workstation and server designs, the memory interface and AGP port in the HDIT North Bridge can also be configured in HDIT Mode to double or even quadruple memory data bandwidth to rates as high as 4.2GB per second.
"With our new HDIT architecture, VIA has once again demonstrated our growing market leadership and ability to deliver creative engineering innovation to the PC platform," commented Dr. Tzu-Mu Lin, Sr. Vice President of Engineering of VIA Technologies, Inc. "It is designed to exceed next generation high bandwidth data traffic requirements within a PC system, but still maintains a flexible system implementation that allows System OEMs to meet different performance and cost requirements in all segments of the PC market."
VIA's HDIT Architecture VIA's HDIT Architecture features a high-performance HDIT North Bridge chip with a high-speed DDR266 memory controller interface, AGP 4X, and support for up to four processors. For high-end workstation and server applications, System OEMs can configure the memory interface in HDIT mode and utilize it in conjunction with HDIT Memory Buffers to boost memory bandwidth to rates of up to 4.2GB per second with a 128-bit data path. The data transfer rate from the HDIT North Bridge to the AGP port and I/O expansion slots can also be increased to speeds of up to 2.1GB per second by configuring the system in HDIT mode and integrating two additional 64-bit HDIT PCI-X companion chips.
To ensure a balanced system architecture, VIA is coupling its HDIT North Bridge chip with a new enhanced legacy-free HDIT South Bridge featuring a wide range of integrated functions including dual ATA-100 EIDE controllers, 8-channel HW accelerated Audio and HSP modem, six port USB, integrated networking, and an LPC (Low Pin Count) bus running at 66MHz.
To overcome the bandwidth limitations of the 32-bit, 33MHz PCI bus, the HDIT North Bridge and HDIT South Bridge are connected with the new high-speed V-Link bus that runs in 66MHz or 133MHz modes and delivers data transfer rates of up to 512MB per second.
"The HDIT V-Link is a high efficiency, low latency bus structure with configurable bandwidth ranges to satisfy different segment system I/O requirements," said Eric Chang, Director of Product Marketing for VIA Technologies, Inc. "The 32-bit, 33MHz PCI bus with a peak bandwidth of 133MB/S, is no longer sufficient as the primary bus between the North Bridge and South Bridge and system expansion for advanced PC systems, which are already being equipped with 1GHz processors. Any high-performance system with leading DRAM technology such as DDR SDRAM would be handicapped when paired with a 32-bit/33MHz PCI South Bridge. The system would not be able to fully benefit from advanced DDR SDRAM because the PCI bus has now become the system bottleneck."
The first VIA HDIT chipset is targeted for sampling early in the first half of 2001, and will be implemented for high-end desktop, workstation, and server applications that support leading processors from both Intel and AMD.
VIA HDIT Architecture System Partition for a Multiprocessor Server:
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