Op de Deutsche site Hardwarelab.de hebben ze wat info gepost over nog een overclcoking device voor je Athlon, genaamd der Powercard. Ik heb hieronder wat tekst neergeplant dat is vertaald via Babel Fish.
There are in the meantime different possibilities, the AMD Athlon to over clocks. It is by Umloeten of different SMD of resistances (Tom's hardware), DIP switch modifications (Trinity Micro), or by active plug-in cards, which completely get along without soldering work on the Athlon circuit board (Tom's hardware). From the active circuit board are not so quite convinced, since on the circuit board of resistances present with the help of relatively high voltage by 5’hm of resistances become ' replaced '. Quite high energy dissipations at the resistances occur. I did not want to risk my Athlon by such practices. I decided therefore to a solution similarly XLV750R, whereby with the original resistance values one operates. Disadvantage of the circuit is that all ' admitted ' of resistances at the Athlon be unsoldered must. This process is to be up-soldered somewhat more easily than the microscopically small SMD of resistances again, nevertheless is a good soldering iron, a calm hand and good eyes forces
The card is put easily on the internal plug of the Athlon circuit board. With the 4 large switches the clock frequency of the processor can be stopped. A rise of the core voltage takes place with the Ír DIP switching hereditary hole on the top right. In order to be able to adjust also the L2 Cache factor, which is however not led on the plug signals, some wires at the Athlon must be soldered on. In the current execution thus the PowerCard is ' chained ' to the Athlon circuit board. In the next execution for this its own plug is used. For adjusting the Cache of factor the Ír DIP serves block on the right down.
[...] The clock frequency can be adjusted to values between 300MHz and 1050MHz. It is possible for Underclocking thereby thus also. With core a voltage of 1.75V I could operate mine Athlon 500 with 800MHz stably, whereby the L2 Cache had to be changed over to factor 1/3.