Ace's Hardware heeft wat handige info gepost over problemen bij de produktie van de K6-III, die nogal last heeft van foutgebakken L2 caches:
Idiot told me some very interesting info about the K6-III. As pointed out in our latest article , L2-caches are very vulnerable to particle contamination. besides cleaner fabs, another way to boost yields of CPU's with ondie L2s is redundant row/column protection. In other words, extra rows and columns are manufactured and bad cells are marked during initial wafer test. Then bad rows and columns are disabled and spare rows and columns are enabled with the result that the SRAM or L2-cache works totally correct after all.
The K6-III had minimal redundancy protection, what proved to be a huge mistake! AMD has learned from the mistake, so this is probaby one reason why the Thunderbird introduction (first Athlon with on-die cache) should face less problems.