Ga'ash Soffer van Voodoo Extreme heeft een artikel in elkaar gedrukt over de EPIC architectuur achter Intel's IA-64 instructieset. Hier een stukje over hetgeen Intel met EPIC (een kruisting tussen RISC en CISC) hoopt te bereiken: heavy parallism...
The key to performance is how many instructions each processor can process in a given time. Current architectures, such as RISC and CISC use a technique called pipelining. Pipelining is the process of starting instructions before others are finished. This way throughput of a sequence of instructions which take 3 clock cycles will only take 1 cycle each, since one is started every clock and by the time the first one finishes, the next one will pop out 1 clock cycle later. Unfortunately, current processors have to optimize the code on the fly in search of ways to increase pipelining, or what one might call "pipelinability". Another technique used is that of parallelism, where instructions can be exectued in parallel. RISC and CISC processors must also search for optimal ways to employ any form of parallelism built into the code.The EPIC idea suggests employs a scheme where the EPIC processor expects the program to arrive with parallelism instructions built in. Hence the name explicitly parallel. Furthermore, EPIC processors must be capable of handling immense parallelism. For this reason, Itanium, and future EPIC processors will feature wide data paths, many pipelines, and quick access to high bandwidth memory.
