Best wel handig proggie. Dit geeft-ie bij mij aan:
SPD dump of Dimm in socket :0
SPD - Number of bytes available :128
SPD - Total bytes of memory device :256
SPD - Revision :18
SPD - Checksum :Faulty
Manufacturer - Name :Micron Technology
Manufacturer - Location :4 ($04)
Manufacturer - Part Number :16LSDT664AG-10B4
Manufacturer - Revision code :40 ($0400)
Manufacturer - Manufacturing date :$9914
Manufacturer - Assembly Serial Number :0055186
Manufacturer - Manufacturer Specific Data :
Memory - Type :Sync Dram
Memory - Row Addresses :12
Memory - Column Addresses :0
Memory - Module Banks :2
Memory - Data Width :64
Memory - Data Width continuation :0
Memory - Voltage interface standard :1
Memory - Cycle time at Max. Supported CAS :8 ns.
Memory - SDRAM Access from Clock at :0 ns.
Memory - DIMM Configuration type :None
Memory - Refresh Rate/Type :Self Refresh, Normal (15.625 us)
Memory - Minimum Clock Delay :1
Memory - Burst Lengths Supported <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/puh2.gif width=15 height=15>age 1 2 4 8
Memory - Banks on Each SDRAM device :4
Memory - CAS Latencies Supported :2 3
Memory - CS Latencies Supported :0
Memory - WE Latencies Supported :0
Memory - Min. Clock Cycle Time @ CL X-1 :12 ns.
Memory - Max. Data Access Time from Clock @ CL X-1 <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/yummie.gif width=15 height=15> ns.
Memory - Min. Clock Cycle Time @ CL X-2 :0 ns.
Memory - Max. Data Access Time from Clock @ CL X-2 :0 ns.
Memory - Minimum Row Precharge Time :20 ns.
Memory - Minimum Row Active to Row Active delay :20 ns.
Memory - Minimum RAS to CAS delay :20 ns.
Memory - Minimum RAS Pulse Width :50 ns.
Memory - Module Bank Density :64 MB.
Memory - Module Total Density :128 MB.
Memory - Speed :100 Mhz
SPD dump of Dimm in socket :1
SPD - Number of bytes available :128
SPD - Total bytes of memory device :256
SPD - Revision :18
SPD - Checksum :OK
Manufacturer - Name :Micron Technology
Manufacturer - Location :4 ($04)
Manufacturer - Part Number :1LSDT1664AG-10CB4
Manufacturer - Revision code :40 ($0400)
Manufacturer - Manufacturing date :$9914
Manufacturer - Assembly Serial Number :0055195
Manufacturer - Manufacturer Specific Data :
Memory - Type :Sync Dram
Memory - Row Addresses :12
Memory - Column Addresses <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/yummie.gif width=15 height=15>
Memory - Module Banks :2
Memory - Data Width :64
Memory - Data Width continuation :0
Memory - Voltage interface standard :1
Memory - Cycle time at Max. Supported CAS :8 ns.
Memory - SDRAM Access from Clock at :6 ns.
Memory - DIMM Configuration type :None
Memory - Refresh Rate/Type :Self Refresh, Normal (15.625 us)
Memory - Minimum Clock Delay :1
Memory - Burst Lengths Supported <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/puh2.gif width=15 height=15>age 1 2 4 8
Memory - Banks on Each SDRAM device :4
Memory - CAS Latencies Supported :2 3
Memory - CS Latencies Supported :0
Memory - WE Latencies Supported :0
Memory - Min. Clock Cycle Time @ CL X-1 :12 ns.
Memory - Max. Data Access Time from Clock @ CL X-1 <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/yummie.gif width=15 height=15> ns.
Memory - Min. Clock Cycle Time @ CL X-2 :0 ns.
Memory - Max. Data Access Time from Clock @ CL X-2 :0 ns.
Memory - Minimum Row Precharge Time :20 ns.
Memory - Minimum Row Active to Row Active delay :20 ns.
Memory - Minimum RAS to CAS delay :20 ns.
Memory - Minimum RAS Pulse Width :50 ns.
Memory - Module Bank Density :64 MB.
Memory - Module Total Density :128 MB.
Memory - Speed :100 Mhz
SPD dump of Dimm in socket :2
SPD - Number of bytes available :128
SPD - Total bytes of memory device :256
SPD - Revision :18
SPD - Checksum :Faulty
Manufacturer - Name :Unknown ID: 0000000000000000
Manufacturer - Location :0 ($00)
Manufacturer - Part Number :1Mx64-10
Manufacturer - Revision code :00 ($0000)
Manufacturer - Manufacturing date :$0000
Manufacturer - Assembly Serial Number :0000
Manufacturer - Manufacturer Specific Data <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/frown.gif width=15 height=15>c)SI 4.98 8Mx8
Memory - Type :Sync Dram
Memory - Row Addresses :12
Memory - Column Addresses <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/yummie.gif width=15 height=15>
Memory - Module Banks :2
Memory - Data Width :64
Memory - Data Width continuation :0
Memory - Voltage interface standard :1
Memory - Cycle time at Max. Supported CAS :8 ns.
Memory - SDRAM Access from Clock at :6 ns.
Memory - DIMM Configuration type :None
Memory - Refresh Rate/Type :Self Refresh, Normal (15.625 us)
Memory - Minimum Clock Delay :1
Memory - Burst Lengths Supported :1 2 4 8
Memory - Banks on Each SDRAM device :4
Memory - CAS Latencies Supported :2 3
Memory - CS Latencies Supported :
Memory - WE Latencies Supported :0
Memory - Min. Clock Cycle Time @ CL X-1 :0 ns.
Memory - Max. Data Access Time from Clock @ CL X-1 <img src=http://192.87.219.67/~femme/wot/forum/interface/smilies/loveit.gif width=15 height=15> ns.
Memory - Min. Clock Cycle Time @ CL X-2 :0 ns.
Memory - Max. Data Access Time from Clock @ CL X-2 :0 ns.
Memory - Minimum Row Precharge Time :20 ns.
Memory - Minimum Row Active to Row Active delay :20 ns.
Memory - Minimum RAS to CAS delay :20 ns.
Memory - Minimum RAS Pulse Width :48 ns.
Memory - Module Bank Density :64 MB.
Memory - Module Total Density :128 MB.
Memory - Speed :100 Mhz