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Bron: Sharky Extreme

Sharky Extreme heeft het derde deel van hun Memory Guide op de site geparkeerd. Je vind er uitleg over termen zoals DRAMs, SRAMs, SDRAMs, FPM en EDO RAMs, pipelining, memory timings enz.

Hier heb je een stuk over Asynchronous vs Synchronous DRAMs:

The timings within the SRAM and DRAM chips were originally controlled by an internal clock that was completely separate from the system clock that the CPU used (asynchronous). This meant that the CPU had to wait for the data to come back from memory, because it didn't 'know' exactly when to expect it. This would be similar to telling someone to go get a pizza and bring it back as soon as it is ready, forcing you to wait around until he (or she) returned. If the memory was particularly slow, an extra 'wait state' had to be programmed in (usually through the BIOS setup) so the CPU wouldn't time out waiting for the data.

In order to make the memory transfers more efficient, designers added a signal pin which allowed the system clock to control the timings (CLK). With both the CPU and memory 'synchronized' to the system clock, the CPU would now know how many clock cycles it would take for the data to be retrieved. This would be like telling someone to get you a pizza, and to meet you back on the corner in 30 minutes. Now you can spend that 30 minutes doing other things.

With a synchronous interface, many of the internal operations of the memory are under the control of the clock signal. This simply means that the operation is triggered by the transition of the CLK pin (usually from high to low). Each operation within the memory chip takes a finite amount of time to complete (in nanoseconds), so by knowing what the clock cycle time is, the number of cycles necessary to complete the operation is known. For example, if an operation requires 25ns and the clock cycle is 10ns, then 3 cycles are necessary to complete the operation. This allows the next operation to begin at the 3rd transition of the clock signal (30ns).

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