Ars-Technica heeft een follow-up gepost van z'n Intel clock-lock artikel, met meer info en reacties van mensen 'die er verstand van hebben':
For those of you who haven't heard yet, Anand and some other sites are reporting that PIIIs are bus-locked. According to Anand, the PIII core works only within a certain range of speeds. Supposedly there is some tolerance here, and the chips aren't locked to one specific MHz rating, but the tolerance is tight enough (±5MHz) that, when combined with a multiplier lock, the chips should be impervious to overclocking.
The fact that the PIII core is not locked to a specific speed, but to a range of speeds, shows that my concerns about the feasibility of building an on-die, temperature-independent bus lock were justified. For those of you who read the earlier article, you'll recall that I stated that any bus-locking scheme implemented on-die would run into heat-related accuracy problems. This appears to be the case on the PIII, though they've got the accuracy problem under control enough to make an on-die bus lock feasible. I have some insight on how Intel might have accomplished this task.
Belangrijke info voor overklokkers dus. Zie Ars Technica voor de rest.