Clive Turvey heeft de PIII KNI instructies ge-reverse-engineered en heeft dit lijstje met info over opcodes al bij elkaar weten te sprokkelen. Dit zegt hij er zelf nog even over :
KNI/MMX2 instructions. I ran into an application on Intel's public FTP site that contains what I believe to be the KNI/MMX2 instruction set. I haven't got the whole encoding figured out, but the following table shows where they fit into the opcode map. The application also makes reference to registers XMM0 thru 7, which I believe will be a set of FP MMX registers that are separate and distinct from the integer registers MM0 thru 7. Given the size of the context space "conveniently" provided by FXSAVE/FXRSTOR (512 bytes), this would allow each register to be 40 bytes in size, or 4 x 80 bit FP / 8 x 40 bit FP. If you look at the instructions you'll see a lot of SS & PS references, I'm not sure if this means single/double precision or primary/secondary registers! In any case Intel's FPUs typically deal with 80 bit FP values and given 8 registers you could easily represent two 4x4 matrices.These are the new instructions: addps, addss, andnps, andps, cmpeqps, cmpeqss, cmpleps, cmpless, cmpltps, cmpltss, cmpneqps, cmpneqss, cmpnleps, cmpnless, cmpnltps, cmpnltss, cmpordps, cmpordss, cmpunordps, cmpunordss, comiss, cvtpi2ps, cvtps2pi, cvtsi2ss, cvtss2si, cvttps2pi, cvttss2si, divps, divss, fxrstor, fxsave, ldmxcsr, maskmovq, maxps, maxss, minps, minss, movaps, movhps, movlps, movmskps, movntps, movntq, movss, movups, mulps, mulss, orps, pavgb, pavgw, pextrw, pinsrw, pmaxsw, pmaxub, pminsw, pminub, pmovmskb, pmulhuw, prefetchnta, prefetcht0, prefetcht1, prefetcht2, psadbw, pshufw, rcpps, rcpss, rsqrtps, rsqrtss, sfence, shufps, sqrtps, sqrtss, stmxcsr, subps, subss, ucomiss, unpckhps, unpcklps & xorps
Vast wel interessant voor hardcore-programmeurs, maar ik snap er weinig van.
