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Chip magicians at work: patching at 45nm

Door Redactie Tweakers.net, zondag 28 oktober 2007 20:07, views: 118.819

Errata and conclusion

However hard Intel works, a chip as complex as Penryn can never be wholly perfect, at least not if the company doesn't put a few extra years of work into it. Some problems are solved using software patches, such as microcode or bios updates. Other problems, usually the ones that are discovered while running random instructions, sometimes aren't fixed at all - either because it is thought that the circumstances are so bizarre that practically no-one will ever encounter them, or because the potential problems are so minute that it simply isn't worth the effort of solving them.

But everything that is found in the labs does get published. For the first commercially available version of the Core 2 Duo, a total of 112 of these so-called 'Errata' are known. Intel uses this term because it thinks the word 'bug' does not apply: bugs must be solved, but most errata aren't really anything to worry about. For example:

With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered. This may cause interrupts whose priority is lower than the initial TPR, but higher than the final TPR, to not be serviced until the interrupt enabled flag is finally set, i.e. by STI instruction. Interrupts will remain pending and are not lost.

This summer, 39 of these issues have been addressed in the new G0 stepping, but a new issue was also identified. In spite of the fact that there are still 74 known 'mistakes' in the chip design, most people will concede that they are not having any problems whatsoever, which means that the people in the validation lab have done a decent job.

* Conclusion

Developing a new processor will easily take three to four years, where the last year prior to the introduction is mostly reserved for testing and perfecting the chip. However, validation does not start at the moment the first silicon returns from the factory, nor does it stop once the product hits the market. Also, it is rare that the processor can be tested in isolation. Usually, the chipset must be tested simultaneously, which makes things even more complicated.

Hence, what we showed in this article is only a small part of the total trajectory, but hopefully it has become clear that there is a huge difference between having a sample and having a commercial product. The fact that two weeks ago, Intel had a machine up on stage that could read the sentence 'Hi, I am Nehalem. I am only three weeks old, and I am already talking' may be encouraging, but in the coming year this chip has to be subjected to an extensive testing trajectory before it will be ready for release.

Intel validation slide
Chronologic overview of the various stages in the validation process
* Plug this story

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Reacties


Waarom is het in het Engels geschreven?

Why the article is written in English?

Om eventueel internationaal publiek naar tweakers.net te trekken / op tweakers.net te bedienen, zeker bij een 'uniek' artikel als dit. Men vertaalt wel vaker als t.net redactie echt iets van belang heeft ondernomen. En het is een vertaling, op pagina 1 staat keurig naar het origineel gelinkt.

En het werkt aangezien het op slashot is verschenen. (De reden dat ik hier terug kwam eig., ik dacht dat ik iets gemist had :X )

Nice article :) Finally, we hear (or at least a part) of what's going on at Intel. It's nice to read something about it, it's quite a special story.

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