Now that you know what EPIC and IA-64 are the time has come to talk about the very first IA-64 processor, known at Intel under the codename Merced, for the public: Itanium. The physical properties of Itanium aren't impressive at all. Six layers of aluminum with a lowly 25 million transistors produced at 0.18 micron, running at a clockspeed not exceeding 800MHz. Even the Pentium III core seems more advanced with its 28 million transistors and a current top speed of 1GHz, let alone the Pentium 4 with a 42 million transistor count at 1,5GHz, still, for a chip that should have been released in 1997, not bad.
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Inside the Itanium core is a lot more interesting, it is capable of processing two 128 bit IA-64 instruction bundles at the same time. This means a maximum of six instructions per clock tick and because some instructions require multiple operations that can be done simultaneously by Itanium, this number of operations per clock tick can rise to 20. For this a small army of execution units and registers is deployed. The 11 execution units and 328 registers can produce a theoretical maximum of 6,4 GFLOPS. This enormous amount of resources enables the Itanium to function parallel as required by the EPIC philosophy. Here is a breakdown of the internal features:
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The Itanium also has on-die cache, consisting of 16KB L1 data, 16KB L1 integer and 96KB L2 cache. This seems rather small for a processor with such features but is amply compensated for by Intel by using L3 cache. 2 or 4MB can be placed on the processor cartridge, connected to the core with a 128 bit bus. Because the cache runs at full speed, total bandwidth to the processor becomes 11,9GB/s for the 800MHz version.
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Naturally the Itanium had to be reliable too, ECC has been applied to virtually every internal processor bus, this enables the identification and correction of errors without the need for a reboot. Errors can be logged too and the processor is capable of recognizing errors in the rest of the system and correct or isolate them. The Itanium does not rely on the motherboard to ensure a stable voltage either. On the side of the big black cartridge that houses the core, an Intel designed voltage regulator, even bigger than the processor itself, should be connected.
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Then there's the problem of old software, although Itanium is a completely new design Intels customers will want to use software that hasn't been ported yet to IA-64 every now and then. To make this possible the Itanium has a hardware decoder for IA-32 that's 100% compatible with current software including MMX and SSE2. Of course the EPIC core can't do anything with these instructions so everything is translated so that the Itanium can execute it and the old software can understand the output.
The chipset the Itanium uses is the Intel 460GX, capable of running with a maximum of four Itanium processors on a dual pumped bus at 133MHz (effectively 266MHz). The chipset can address a maximum of 64GB of memory with a choice between PC100 SDRAM and PC1600 DDR SDRAM. An integrated ethernet card and AGP 4x are optional. For bigger stuff you'll have to go to different companies like NEC, IBM, HP and Compaq, they are working on 16- and 32-way Itanium chipsets. For such a 32-way system you'll have to break the piggybank btw, an 800MHz Itanium with 4MB L3 cache will cost over 4000 dollars. It's clear the Itanium is absolutely not a desktop processor 
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