Voor het heftige werk heeft Hitachi een servertje in de planning die is voorzien van maar liefst 32 Itanium processors. Het systeem krijgt waarschijnlijk 64Mb cache memory en weet dankzij 32 PC133 DIMM slots ook de meest dwaze upgraders in hun behoeften te bevredigen (thanks McMiGHtY voor de tip):
By using its own chip set and mainframe multiprocessing schemes, Hitachi will be able to deploy eight- and 32-way Itanium systems several months after the first standard two- and four-way systems start shipping, company officials here said.
The hallmark of the Hitachi system is its large, hierarchical cache memory scheme. For each symmetric-multiprocessing (SMP) node, which contains four Itanium processors, Hitachi is leaning toward using as much as 64 Mbytes of cache, though 32 Mbytes is also being considered, said Toshihiro Tsukishima, marketing manager for the platform systems planning department at Hitachi's Enterprise Server Division (Ebina-shi, Japan).
"We believe using a huge cache memory outside the CPU will help speed the efficiency of applications," he said. "Without such a large cache, we'd have a long delay for data coming from main memory."
The level-three cache memory will send data to two memory controllers governing a bank of main memory at each node. For main memory, Hitachi will use a series of 1-Gbyte dual in-line memory modules consisting of 133-MHz SDRAMs, also known as PC133 SDRAMs. There will be a total of 32 DIMM slots — or 32 Gbytes of storage capacity — for each node.
Each node within the multiple-SMP scheme will have a "node controller" to manage the flow of data among the Itanium processors, cache, PCI bridge chips and a high-speed crossbar switch that ties together as many as eight nodes. Each of these controllers has an external tag memory, which helps monitor and control the data moving into the L3 cache.
Voor meer sappige info kun je terecht in dit artikel van EETimes.