CPU Review heeft een artikel geschreven over Intel's toekomstplannen wat betreft de ontwikkeling van nieuwe geheugenstandaarden. Intel wil met de vorming van de 'Next Generation DRAM alliance' duidelijk een tweede Rambus fiasco voorkomen:
We can never have too much bandwidth. Current processor performance is significantly limited by memory bandwidth. Future 1Ghz+ processors will be even more limited in their performance by slow front side bus speeds.
The acceptance of a new Jedec backed standard for high-bandwidth memory interfacing is far more likely when it is backed by all the major players - without the disadvantage of (an expensive) royalty being involved.
Intel appears to have learned from its Rambus experiences, and hopefully will reach a consensus with memory manufacturers as to what the new standard memory interfacing technology should be.