Ik lees bij HardOCP een errug heldere verklaring (NOT) van Intel over wat er fout gaat met het derde Rambus slot bij i820 moederplanken:
Low launch voltage is due to superposition of:
- Back-2-Back Reads to Different Devices (device A & device B).
- Specific Data Patterns.
- Position Sensitivity of EACH Device Being Accessed.Low launch voltage exceeds the specification and derates RDRAM drive strength. Launch Voltage is the voltage of a net when the output buffer begins driving.
Output buffer derating combined with architectural B-2-B handoff and reflections + crosstalk causes failure. All elements simultaneously required to cause failure. [break] Okay, sure. Gelukkig heeft Intel een oplossing voorhanden, en hoe: [/break] - Build and validate 2 RIMM Boards.
- Any 3RIMM boards should be redesigned for 2RIMM only.
- 2RIMM Design Update 1.06 is now available; follow guidelines for respin of boards to 2RIMM only.
- PCG will continue to investigate other solutions for reducing accumulation of reflections. [break] Oftewel: sloop het derde slot eraf en je bent klaar... Verder bij HardOCP nog wat info over voltages en package versies van de nieuwe Coppermine: [/break] There will be two version of the Coppermine CPU that I know of so far. One is SC242 (Slot-1); the other is FC-PGA (Socket 370). The FC-PGA version of Coppermine has changed it's pin out definition compared to Celeron, so the current Celeron Socket370 boards will not run the Current Coppermine architecture. But this does not mean that only the 810e platform can run the FC-PGA Coppermine. Our Slot-1 Coppermine was VERY much at home on our BX chipset board. Once the pin configuration is worked out we might very well see BX Chipset boards able to run the Coppermine in a Socket370. Also it seems as if slower than 666MHz Coppermines will run at 1.6 volts while the faster CPUs will use a 1.65 voltage.
