Chip ontwerpers gaan in hun zoektocht naar steeds hogere performance het pad in van heavy parallism, zo bericht EETimes. Intel kiest hierbij voor het sterk compiler-afhankelijke instruction-level parallelism (ILP), terwijl IBM daar nog een flinke schep tegenaan gooit door twee cores in één processor te verenigen, het zogenaamde chip multiprocessing. Compaq / API pakken het weer anders aan: middels thread-level parallelism (TLP) werkt één enkele processor als een virtueel quad processor systeem:
Slater and other analysts said that while Intel's Itanium is expected to fare well when it debuts next year, the use of instruction-level parallelism may be coming to an end for new architectures as designers begin to see the advances in chip- and thread-level parallelism that IBM, Compaq and others are leveraging.
Indeed, keynoter John Hennessy, co-developer of the first commercial RISC chip and professor of electrical engineering and computer science at Stanford University, cited a looming transition away from ILP.
"These techniques are getting ever more complicated. I don't see any performance wall, but there are steeper slopes ahead," he said, noting the complexity of using techniques such as trace caching and value speculation. Bigger advances will come as designers embrace parallelism through multithreading, but that requires a significant transition, he added.
"We are entering a domain where designers need to employ multiple threads, and that requires software support," Hennessy said. "That means we have to help software guys think of new ways to deal with parallelism. It's time we get started on the process of moving to multithreaded software models."