Ik kwam bij Ace's Hardware wat leuke info tegen over IBM's vijfde generatie PPC design:
"The IBM RS64 III superscalar RISC microprocessor integrates high bandwidth, short pipe depth with low latency, large caches, and zero-cycle branch mispredict penalty into a fully scalable, 64-bit, PowerPC-compatible symmetric multiprocessor (SMP) implementation." Thus one clearly sees that IBM wants these chips to be optimized in a server enviroment. The scary point is that, although optimized to be a low latency design like K6 and G4 the RS64 III chip still achieves a sweeping 450MHz with IBM's CMOS 7S process. The L1 is 128 KB each for both data and instruction, second only to PA-8500. (hmmmm what will a P6, K6 or K7 core do with this kind of L1?) The scary part is the 1 cycle load to use latency for the L1 data cache, which is something only mp6 seems to have in the IA32 arena. It also integrates L2 tags onto the chip like G3/4, and K7. L2 is DDR-SRAMs which provide up to 14.4 GB/sec bandwidth. The die size is 140mm^2, on par with Intel's celeron. However the most striking feature is the 1 or 0 branch-misprediction penalty, the biggest potential performance bottleneck to both P6, K7, and Alpha other than memory latency. All this in a 4 issue machine with 5 pipeline stages.
Check Ace's Hardware voor meer info over dit procje.