Over bij Ars Technica hebben ze een uitgebreid artikel geschreven over dit hele SMP / Dual Celeron gedoe, over hoe en wanneer het onstaan is en hoe het nu eigenlijk werkt. Hier heb je een plak:
To understand what's going on here, you need to know a little bit about dual-processor systems. When you've got two processors, one of the main issues you have to work out is who gets control of the bus and when (this issue is called bus arbitration). Back in the 386 days, when you only had one processor on the bus calling the shots, bus arbitration wasn't an issue. The old Intel CPUs had a bus request pin (BREQ#) that would go low when the CPU needed the bus, and that's all you needed to worry about. In today's world, things are a bit more complicated.
