Idiot (zo noemt-ie zich) van Ace's Hardware heeft een paar opmerkingen gepost over het artikel van The Microprocessor Report waarin een aantal zwakheden van het K7 design worden besproken. Als we Ace's Hardware moeten geloven dan zit alles ok bij de K7:
For the BHT part on Branch Predictor, AMD has said that K6's was an overkill and this choice of BHT size will help the MHz ramp and reduce die area. Next the register files in K7 can do lots of reads and writes in one cycle namely 9 read an 8 write for their integer future file and register file (IFFRF) and 5 read 5 write for the FPU registers. As for not having bypass circuitry, the FPU register can actually do a write on a register that's being read in the same cycle, so this becomes a non-issue for FPU.
As for the schduler depth, since K7 will be fed very well by its 64bit/16 byte multi-ported L2 bus, it should be full most of the time according to MPR and the centralized scheduler could keep 72 MOP on the fly. For the on-die tag, although it might only support 512KB 2-way, the fast lookup speed will do much good for the hit/miss ratio. Also, this feature is even at work when K7 is using additional off-chip tag rams.
We zullen zien (over een paar weken).