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VLIW future

EETimes heeft een artikel met stuff van Transmeta's president David Ditzel, die wat ouwehoerd over VLIW (Very Long Instruction Word), RISC, CISC en meer van dat soort lekkernijen:

In his speech, Ditzel told some 300 conference attendees that RISC may be reaching the end of its "learning curve" after 20 years of use. He noted that RISC, which originally began as a rebellion against complexity, has itself become bogged down by massive instruction sets and large die sizes.

"It was really fun in the early days; almost every computer company had a RISC chip," he said. "You did it because you could and you needed only a small design team."

Nowadays, that's no longer the case, Ditzel argued. "Today [in RISC] we have large design teams and long design cycles," he said. "The performance story is also much less clear now. The die sizes are no longer small. It just don't seem to make as much sense."

The result is the current crop of complex RISC chips. "Superscalar and out-of-order execution are the biggest problem areas that have impeded performance [leaps]," Ditzel said. "The MIPS R10,000 and HP PA-8000 seem much more complex to me than today's standard CISC architecture, which is the Pentium II. So where is the advantage of RISC, if the chips aren't as simple anymore?"

Moving forward, though, Ditzel hasn't sounded a death knell for RISC. Indeed, he sees good opportunities for the Sparc and Alpha architectures, particularly if Intel's upcoming Merced CPU takes time to gain widespread support.

Door Femme Taken


03-12-1998 • 20:07

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