Intel Itanium sneak preview

Tahoe, the codename for Intels new ISA (Instruction Set Architecture) based on EPIC has received the official name Intel Architecture 64. In IA-64 the instruction bundles are 128 bit and contain a maximum of three instructions of 41 bit each, as opposed to IA-32 which did not have fixed instruction length. These three instructions use 123 bit so that leaves 5 bit for extra information about the instruction bundle which helps the processor use its resources more efficiently.


Apart from the large step from CISC to EPIC Intel made the leap from 32 to 64 bit. What exactly does this mean? First, the processor can work with values that are 64 bit (8 byte), this means larger numbers and greater accuracy than 32 bit processors. Second, the address bus can be expanded to 64 bit which means the IA-64 architecture can address a maximum of 18 Exabyte of memory. The 4GB that Windows 98 can use and even the 64GB that Windows 2000 Datacenter Server in combination with Pentium III Xeon processors can address pale in comparison.

Additionally, software pipelining has been added in IA-64. This feature that is also called register rotation is especially useful for actions that have to be applied to different variables, like in while and for loops that every programmer knows. Instead of applying the same actions on a row of values one by one the processor simply moves the values in the registers one place. In reality the names of the registers are changed and the data is not physically moved but the effect is the same: multiple variables in different stadia of manipulation are present at the same time. This saves a lot of time because the code is smaller and less is needed from memory.



The main principle behind IA-64 is functioning in parallel; an IA-64 processor must be capable of doing a lot of things simultaneously. For this not only do you need a lot of execution units but also a whole load of registers. The IA-32 processor that we know now generally have 32 or fewer of these registers, IA-64 processors will need over 256. Apart from being able to work in parallel another advantage of the many registers lies in the fact that complex calculations with many values can be executed quickly, without needing to fall back on the cache.

The performance of an IA-64 processor is enormously dependent on its compiler. That is a disadvantage because a compiler is very complex to program, it has to take an enormous amount of factors into account to analyze the source code and produce the instruction bundles. Someone writing such a compiler must know the processor architecture inside-out. The compilers for IA-64 have been under development for almost as long as the architecture itself but in spite of all the effort they won't be optimal when released. By means of optimizations and new ideas for smarter compilers the performance of IA-64 processors will be able to increase considerably over the years.