Geen idee of dit waar is, maar het zou wel leuk zijn: JC kreeg info over iemand die de L2 cache chips van z'n Athlon heeft vervangen met DDR SRAM:
Quick scoop, I'll integrate this into an update later: Daiki knows of someone who chunked faster SRAM ("this Athlon is Athon500@835 with DDR-SRAM Full speed L2 ") of some sort in place of the L2 on a 830MHz (overclocked) Athlon. Reportedly, the latency of the cache was 23 cycles. According to Daiki, performance with this was very fast, allowing the Athlon to outperform the Coppermine even in the "Athlon-killing" Super-Pi benchmark .... If this is true, it's very promising. The Thunderbird will have far superior caching compared to this setup, as the latency will be probably better than halved (and hopefully, the cache bandwidth will be improved, but even without that it should be fairly sweet). More on this later, I guess.