The Register heeft weer wat leuke info opgevist. Geen idee of dit waar is...
Sources close to Intel have suggested that the Mendocino design, which saved the Celeron from utter oblivion, has 256K cache designed in, not just the 128K cache, as widely advertised.
According to the source, Cadence was called in after the original Celeron performed disastrously and designed the Mendocino core. The Intel source, based in Israel, said that the external design was good, but Intel did not want to implement everything all at once. That suggests that Intel may well enable the other 128K of trannies at a time best known to it.
No one from either the Intel or Cadence press offices was available at press time.