In BIOS release 7G several new options were added to the "CPU and PCI Bus Control" page. These are described below:
- Support AMD AthlonXP 2100+ CPU.
- Fix CPU fan N/A problem for specific low speed CPU fan.
- HPT 37x BIOS version 2.0.1024.The RAID function is for KR7A-RAID only. This BIOS version is also for non RAID boards and HPT BIOS will be automatically disabled while RAID controller chip not detected.
- BIOS compile date: 4/12/2002.
It is not clear how this differs from the PCI Delay Transaction option
- PCI Master Read Caching (Disable/Enable) This allows the controller to read data ahead of the PCI master from memory into the CPU L2 cache, especially during burst cycles (memory read line and other advanced commands). This boosts the performance of PCI masters at the expense of using some of the CPU's L2 cache. Users of the Duron processor (which has a smaller L2 cache) should leave this as disabled as the loss of cache would reduce performance. Users of the Athlon processors (Thunderbird, XP) can enable this to improve PCI performance (eg. disk performance) but may still suffer a CPU performance penalty. You should experiment to see what works best for you.
- PCI Master Bus Timeout (Disable/001/010/011/100/101/110/111) Determines the number of PCI clock cycles (in increments of 32 PCICLK cycles) the controller waits before disconnecting a device if the first data access is not completed. This option can often be used to resolve issues with data corruption on disks and crackling with soundcards.
- Master Priority Rotation Control (Disable/01/10/11) This controls how quickly the CPU can access the PCI bus. If you choose 01 then the CPU will always be granted access right after the current master transaction completes, irrespective of how many other PCI bus masters are in the queue. This provides the quickest CPU access to the bus but the poorest performance for PCI devices. If you choose 10 then the CPU gets access after the current and next access, and if you choose 11 then the CPU must wait for the current access plus the next two. Whatever you choose, the CPU always get access after a maximum of three PCI master grants. Master Delay Transaction (Disable/Enable)