Intel Willamette preview

De mannen van HardwareCentral hebben ze hun Intel Willamette preview weer bijgewerkt. De meest recente informatie over de Willamette, de opvolger van de P3, is er nu te vinden :

New SIMD instructions introduced in the Willamette CPU include floating-point SIMD instructions and integer SIMD instructions. They aim to do away with one of the major bottlenecks found in today’s x86 CPUs: the x87 FPU, the floating-point unit of an x86 CPU.

If we take a closer look at the performance of the x87 FPU, we can see that it is severely restricted by the demand for compatibility with the aging x87 FPU standard. Improving performance would not be easy if we stick by its original design. Using SSE2 to bypass the x87 FPU completely is a good way to circumvent the bottleneck. Even better, if Intel can find enough support among the software developers and give them enough incentive to start using SSE2 for doing floating point operations, the Willamette’s SSE2 FPU will offer FPU performance which is approximately ten times as fast as that of the x87 FPU.

[...] With the introduction of a 20-stage pipeline in the Willamette, which is the longest pipeline ever implemented in an x86 CPU, Intel has found a way to make the Willamette run at very high clockspeeds, in excess of 1.5 GHz. A longer pipeline can be used to increase a CPU’s clockspeed by trading off the number of stages against clockcycle duration. As an instruction is processed in stages, a 10-stage pipeline divides an instruction into 10 steps and takes 10 clockcycles to process the entire instruction; during every clockcycle a stage of the instruction is finished. Due to its 20-stage pipeline Willamette takes 20 clockcycles to finish one instruction, so very little processing is done within a single clockcycle and the clockcycle can be very short.